Siemens EF 88H Series Manuel d'utilisateur télécharger pdf (Page 42)

Semiconductor Group 5 - 7

On-Chip Peripheral Components

A/D Converter Timing

After a conversion has been started (by a write to ADDATL, external start by P6.0/ADST

or in

continous mode) the analog input voltage is sampled for 4 clock cycles. The analog source must be

capable of charging the capacitor network of appr. 50 pF to full accuracy in this time. During this

period the converter is susceptable to spikes and noise at the analog input, which may cause wrong

codes at the digital outputs. Therefore RC-filtering at the analog inputs is recommended (see figure

5-2 below).

Conversion of the sampled analog voltage takes place between the 4th an 14th clock cycle.

Figure 5-2

Recommended RC-filtering at the Analog Inputs

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Siemens EF 88H Series Manuel d'utilisateur Page 42