Siemens EF 88H Series Manuel d'utilisateur télécharger pdf (Page 29)

Semiconductor Group 4 - 4

4.2 Hardware Power Down Reset Timing

Following figures are showing the timing diagrams for entering (figure 4-1) and leaving (figure 4-2)

the Hardware Power Down Mode. If there is only a short signal at pin HWPD

(i.e. HWPD is sampled

active only once), then a complete internal reset is executed. Afterwards the normal program

execution starts again (figure 4-3).

Note:

Delay time caused by internal logic is not included.

The Reset

pin overrides the Hardware Power Down function, i.e. if reset gets active during

Hardware Power Down it is terminated and the device performs the normal reset function. Thus, pin

Reset

has to be inactive during Hardware Power Down Mode.

System Reset

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Siemens EF 88H Series Manuel d'utilisateur Page 29