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PROFIBUS Interface Center

SPC3

Page 8 V1.3 SPC3 Hardware Description

2 Function Overview

The SPC3 makes it possible to have a price-optimized configuration of intelligent PROFIBUS-DP slave

applications.

The processor interface supports the following processors:

Intel: 80C31, 80X86

Siemens: 80C166/165/167

Motorola: HC11-,HC16-,HC916 types

In SPC3, the transfer technology is integrated (Layer 1), except for analog functions (RS485 drivers), the

FDL transfer protocol (Fieldbus Data Link) for slave nodes (Layer 2a), a support of the interface utilities

(Layer 2b), some Layer 2 FMA utilities, and the complete DP slave protocol (USIF: User Interface, which

makes it possible for the user to have access to Layer 2). The remaining functions of Layer 2 (software

utilities and management) must be handled via software.

The integrated 1.5k Dual-Port-RAM serves as an interface between the SPC3 and the

software/application. The entire memory is subdivided into 192 segments, with 8 bytes each. Addressing

from the user takes place directly and from the internal microsequencer (MS) by means of the so-alled base

pointer. The base-pointer can be positioned at any segment in the memory. Therefore, all buffers must

always be located at the beginning of a segment.

If the SPC3 carries out a DP communication the SPC3 automatically sets up all DP-SAPs. The various

telegram information is made available to the user in separate data buffers (for example, parameter setting

data and configuration data). Three change buffers are provided for data communication, both for the

output data and for the input data. A change buffer is always available for communication. Therefore, no

resource problems can occur. For optimal diagnostics support, SPC3 has two diagnostics change buffers

into which the user inputs the updated diagnostics data. One diagnostics buffer is always assigned to SPC3

in this process.

The bus interface is a parameterizable synchronous/asynchronous 8-bit interface for various Intel and

Motorola microcontrollers/processors. The user can directly access the internal 1.5k RAM or the parameter

latches via the 11-bit address bus.

After the processor has been switched on, procedural-specific parameters (station address, control bits, etc.)

must be transferred to the Parameter Register File and to the mode registers.

The MAC status can be scanned at any time in the status register.

Various events (various indications, error events, etc.) are entered in the interrupt controller. These

events can be individually enabled via a mask register. Acknowledgement takes place by means of the

acknowledge register. The SPC3 has a common interrupt output.

The integrated Watchdog Timer is operated in three different states: ‘Baud_Search’, ‘Baud_Control,’ and

‘DP_Control’.

The Micro Sequencer (MS) controls the entire process.

Procedure-specific parameters (buffer pointer, buffer lengths, station address, etc.) and the data buffer are

contained in the integrated 1.5kByte RAM that a controller operates as Dual-Port-RAM.

In UART, the parallel data flow is converted into the serial data flow, or vice-versa. The SPC3 is capable of

automatically identifying the baud rates (9.6 kBd - 12 MBd).

The Idle Timer directly controls the bus times on the serial bus cable.

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Siemens SPC3 Manuel d'utilisateur Page 10

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